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rev. 1.2 12/09 copyright ? 2009 by silicon laboratories si840x si840x b idirectional i 2 c i solators with u nidirectional d igital c hannels features applications description the si840x series of isolators are single-package galvanic isolation solutions for i 2 c and smbus serial port applic ations. these products are based on silicon labs proprietary rf isolation technology and offer shorter propagation delays, lower power consum ption, smaller installed size, and more stable operation with temperature and age versus opto couplers or other digital isolators. all devices in this family include hot-swap, bidirectional sda and scl isolation channels with op en-drain, 35 ma sink capa bility that operate to a maximum frequency of 1.7 mhz. the 8-pin version (si8400) supports bidirectional sda and scl isolation; the si8401 supports bidirectional sda and unidirectional scl isolation, and the 16-pin version (si8405) features two unidirectional isolation channels to support additional system signals, such as an interrupt or reset. all versions contain protection circuits to guard against data errors when an unpowered device is inserted into a powered system. small size, low installed cost, lo w power consumption, and short propagation delays make the si840x family the optimum solution for isolating i 2 c and smbus serial ports. safety regulatory approval ? independent, bidirectional sda and scl isolation channels ?? open drain outputs with 35 ma sink current ?? supports i 2 c clocks up to 1.7 mhz ? unidirectional isolation channels support additional system signals (si8405) ? up to 2500 v rms isolation ? wide operating supply voltage: 3.0 to 5.5 v ? ul, csa, vde recognition ? operating temperature range ?40 to +125 c max ? transient immunity: 25 kv/s ? compact so-8 and so-16 narrow-body packages ? rohs compliant ? isolated i 2 c buses ? power over ethernet ? motor control systems ? hot-swap applications ? intelligent power systems ? isolated smps systems with pmbus interfaces ? ul 1577 recognized ?? 2500 v rms for 1 minute ? csa component notice 5a approval ?? iec 60950, 61010 approved ? vde certification conformity ?? iec 60747-5-2 (vde0884 part 2) pin assignments bidirectional isolator channel bidirectional isolator channel asda bsda ascl bscl agnd bgnd avdd bvdd si8400 1 2 3 4 8 7 6 5 bidirectional isolator channel unidirectional isolator channel asda bsda ascl bscl agnd bgnd avdd bvdd si8401 1 2 3 4 8 7 6 5 bidirectional isolator channel avdd nc bvdd nc nc nc adout bdin asda bsda unidirectional isolator channel ascl bscl adin bdout si8405 agnd bgnd unidirectional isolator channel bidirectional isolator channel 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16
si840x 2 rev. 1.2
si840x rev. 1.2 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1. test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.2. typical performance char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.1. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3. device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1. device startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2. under voltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3. input and output c haracteristics for non-i 2 c digital channels . . . . . . . . . . . . . . . . 16 4. layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1. supply bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2. rf radiated emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3. rf, magnetic, and comm on mode transient immunity . . . . . . . . . . . . . . . . . . . . . . 18 5. typical application o verview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1. i 2 c background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2. i 2 c isolator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3. i 2 c isolator design constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4. i 2 c isolator design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6. errata and design migration guid elines (revision a only) . . . . . . . . . . . . . . . . . . . . . . 22 6.1. power supply bypass capacitors (revision a only) . . . . . . . . . . . . . . . . . . . . . . . .22 7. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9. package outline: 8-pin narrow body so ic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 10. landing pattern: 8-pin na rrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 11. package outline: 16-pi n narrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 12. landing pattern: 16-pin na rrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 13. top marking: 8-pin narrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 14. top marking: 16-pin narrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
si840x 4 rev. 1.2 1. electrical specifications table 1. si840x power characteristics* 3.0 v < vdd < 5.5 v. ta = ?40 to +125 c. typical specs at 25 c (see figures 2 and 16 for test diagrams.) parameter symbol test condition min typ max unit si8400/01 supply current avdd current bvdd current idda iddb all channels = 0 dc ? ? 4.2 3.9 6.3 5.9 ma ma avdd current bvdd current idda iddb all channels = 1 dc ? ? 2.3 1.9 3.5 2.9 ma ma avdd current bvdd current idda iddb all channels = 1.7 mhz ? ? 3.2 2.9 4.8 4.4 ma ma si8405 supply current avdd current bvdd current idda iddb all non-i 2 c channels = 0 all i 2 c channels = 1 ? ? 3.2 2.9 4.8 4.4 ma ma avdd current bvdd current idda iddb all non-i 2 c channels = 1 all i 2 c channels = 0 ? ? 6.2 6.0 9.3 9.0 ma ma avdd current bvdd current idda iddb all non-i 2 c channels = 5 mhz all i 2 c channels = 1.7 mhz ? ? 4.7 4.5 7.1 6.8 ma ma *note: all voltages are relative to respective ground.
si840x rev. 1.2 5 table 2. si8400/01/05 electrical characteristics for bidirectional i 2 c channels 1 3.0 v < vdd < 5.5 v. ta = ?40 to +125 c. typical specs at 25 c unless otherwise noted. parameter symbol test condition min typ max unit logic levels side a logic input threshold 2 logic low output voltages 3 input/output logic low level difference 4 i 2 cv t (side a) i 2 cv ol (side a) i 2 c ? v (side a) isdaa = iscla = 3.0 ma isdaa = iscla = 0.5 ma 450 650 550 50 ? ? ? ? 780 910 825 ? mv mv mv mv logic levels side b logic low input voltage logic high input voltage logic low output voltage i 2 cv il (side b) i 2 cv ih (side b) i 2 cv ol (side b) isclb = 35 ma ? 2.0 ? ? ? ? 0.8 ? 400 v v mv scl and sda logic high leakage isdaa, isdab iscla, isclb sdaa, scla = vssa sdab, sclb = vssb ?2.010a notes: 1. all voltages are relative to respective ground. 2. v il < 0.450 v, v ih > 0.780 v. 3. logic low output voltages are 910 mv max from ?10 to 125 c at 3.0 ma. logic low output voltages are 955 mv max from ?40 to 125 c at 3.0 ma. logic low output voltages are 825 mv max from ?10 to 125 c at 0.5 ma. logic low output voltages are 875 mv max from ?40 to 125 c at 0.5 ma. see ?an375: design considerations for isolating an i 2 c bus or smbus? for additional information. 4. i 2 c ? v (side a) = i 2 cv ol (side a) ? i 2 cv t (side a). to ensure no latch-up on a given bus, i 2 c ? v (side a) is the minimum difference between the output logic low level of the driving device and the input logic threshold. 5. side a measured at 0.6 v.
si840x 6 rev. 1.2 pin capacitance sdaa, scla, sdab, sdbb ca cb ? ? 10 10 ? ? pf pf timing specifications (measured at 1.40 v unless otherwise specified) maximum i 2 c bus frequency fmax ? ? 1.7 mhz propagation delay 5 v operation side a to side b rising 5 side a to side b falling 5 side b to side a rising side b to side a falling 3.3 v operation side a to side b rising 5 side a to side b falling 5 side b to side a rising side b to side a falling tphab tplab tphba tplba tphab tplab tphba tplba no bus capacitance, r1 = 1400, r2 = 499, see figure 2 r1 = 806 r2 = 499 ? ? ? ? ? ? ? ? 25 15 20 9.0 28 13 20 10 29 22 30 12 35 18 40 15 ns ns ns ns ns ns ns ns pulse width distortion 5v side a low to side b low 5 side b low to side a low 3.3 v side a low to side b low 5 side b low to side a low pwdab pwdba pwdab pwdba no bus capacitance, r1 = 1400, r2 = 499, see figure 2 r1 = 806, r2 = 499 ? ? ? ? 9.0 11 15 11 15 20 22 30 ns ns ns ns table 2. si8400/01/05 electrical characteristics for bidirectional i 2 c channels 1 (continued) 3.0 v < vdd < 5.5 v. ta = ?40 to +125 c. typical specs at 25 c unless otherwise noted. parameter symbol test condition min typ max unit notes: 1. all voltages are relative to respective ground. 2. v il < 0.450 v, v ih > 0.780 v. 3. logic low output voltages are 910 mv max from ?10 to 125 c at 3.0 ma. logic low output voltages are 955 mv max from ?40 to 125 c at 3.0 ma. logic low output voltages are 825 mv max from ?10 to 125 c at 0.5 ma. logic low output voltages are 875 mv max from ?40 to 125 c at 0.5 ma. see ?an375: design considerations for isolating an i 2 c bus or smbus? for additional information. 4. i 2 c ? v (side a) = i 2 cv ol (side a) ? i 2 cv t (side a). to ensure no latch-up on a given bus, i 2 c ? v (side a) is the minimum difference between the output logic low level of the driving device and the input logic threshold. 5. side a measured at 0.6 v.
si840x rev. 1.2 7 table 3. electrical characteristics for unidirectional non-i 2 c digital channels (si8405) 3.0 v < vdd < 5.5 v. ta = ?40 to +125 c. typical specs at 25 c parameter symbol test condition min typ max unit high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0 . 8v high level output voltage v oh loh = ?4 ma avdd, bvdd ?0.4 4.8 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ?? 1 0 a output impedance 1 z o ?8 5? ? timing characteristics maximum data rate 0 ? 10 mbps minimum pulse width ? ? 40 ns propagation delay t phl , t plh see figure 1 ? ? 20 ns pulse width distortion |t plh - t phl | pwd see figure 1 ? ? 12 ns propagation delay skew 2 t psk(p-p) ? ? 20 ns channel-channel skew t psk ? ? 10 ns output rise time t r c 3 =15pf see figure 1 and figure 2 ?4 . 06 . 0n s output fall time t f c 3 =15pf see figure 1 and figure 2 ?3 . 04 . 3n s notes: 1. the nominal output impedance of a non-i 2 c isolator driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination re sistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a fa ctor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature.
si840x 8 rev. 1.2 figure 1. propagation delay timing (non-i 2 c channels) 1.1. test circuits figure 2 depicts the timing test diagram. figure 2. simplified timing test diagram table 4. electrical characteristics for all i 2 c and non-i 2 c channels 3.0 v < vdd < 5.5 v. ta = ?40 to +125 c. typical specs at 25 c parameter symbol test conditions min typ max units vdd undervoltage threshold vdduv+ avdd, bvdd rising 2.15 2.3 2.5 v vdd negative-going lockout hysteresis vddh? avdd, bvdd falling 45 75 95 mv common mode transient immunity cmti v i =v dd or 0 v ? 25 ? kv/s shut down time from uvlo t sd ?3.0?s start-up time * t start ?1540s *note: start-up time is the time period from the appl ication of power to valid data at the output. typical input t plh t phl typical output t r t f 90% 10% 90% 10% 1.4 v 1.4 v avdd nc bvdd nc nc nc adout bdin asda bsda ascl bscl adin bdout agnd bgnd si840x c 1 c 1 c 3 r 1 r 1 r 2 r 2 c 3 c 2 c 2
si840x rev. 1.2 9 1.2. typical perfor mance characteristics the typical performance characteristics de picted in the following diagrams are for information purposes only. refer to tables 1, 2, 3, and 4 fo r actual specification limits. figure 3. i 2 c side a pulling down (1100 ? pull-up) figure 4. i 2 c side b pulling down figure 5. i 2 c side b pulling up, side a following figure 6. i 2 c side a pulling up, side b following figure 7. non i 2 c channel propagation delay vs. temperature side a side b side b side a side b side a side b side a 5 6 7 8 9 10 -40 -20 0 20 40 60 80 100 120 temperature (degrees c) delay (ns) rising edge falling edge
si840x 10 rev. 1.2 table 5. absolute maximum ratings 1 parameter symbol min typ max unit storage temperature 2 t stg ?65 ? 150 oc ambient temperature under bias t a ?40 ? 125 oc supply voltage (revision a) 3 v dd ?0.5 ? 5.75 v supply voltage (revision b) 3 v dd ?0.5 ? 6.0 v input voltage v i ?0.5 ? v dd + 0.5 v output voltage v o ?0.5 ? v dd + 0.5 v output current drive (non-i 2 c channels) i o ??10ma side a output current drive (i 2 c channels) i o ??15ma side b output current drive (i 2 c channels) i o ??75ma lead solder temperature (10 s) ? ? 260 oc maximum isolation voltage (1 s) ? ? 3600 v rms notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to conditions as specified in the operational sections of this data sheet. 2. vde certifies storage temper ature from ?40 to 150 c. 3. see "8.ordering guide" on page 25 for more information. table 6. regulatory information* csa the si840x is certified under csa component acceptanc e notice 5a. for more details, see file 232873. vde the si840x is certified according to iec 60747-5-2. for more details, see file 5006301-4880-0001. ul the si840x is certified under ul15 77 component recognition program. for more details, see file e257455. *note: regulatory certifications apply to 2.5 kv rms rated devices which are production tested to 3.0 kv rms for 1 sec. for more information, see "8.ordering guide" on page 25.
si840x rev. 1.2 11 table 7. insulation and safety-related specifications parameter symbol test condition value unit nb soic-8 nb soic-16 nominal air gap (clearance) 1 l(1o1) 4.9 4.9 mm nominal external tracking (creepage) 1 l(1o2) 4.01 4.01 mm minimum internal gap (internal clearance) 0.008 0.008 mm tracking resistance (comparative tracking index) cti din iec 60112/vde 0303 part 1 >175 >175 v resistance (input-output) 2 r io 10 12 10 12 ? capacitance (input-output) 2 c io f = 1 mhz 1.0 2.0 pf input capacitance 3 c i 4.0 4.0 pf notes: 1. the values in this table correspond to the nominal creepage and clearance values as detailed in ?9. package outline: 8-pin narrow body soic? and ?11. pa ckage outline: 16-pin narrow body soic?. vde certifies the clearance and creepage limits as 4.7 mm minimum for the nb soic-8 package and 4.7 mm minimum for the nb soic-16 package. ul does not impose a clearance and creepage minimum for co mponent level certifications. csa certifies the clearance and creepage limits as 3.9 mm minimum for the nb soic-8 package and 3.9 mm minimum for the nb soic-16 package. 2. to determine resistance and capacitance, the si840x, so-16, is converted into a 2-terminal device. pins 1?8 (1-4, so- 8) are shorted together to fo rm the first terminal and pins 9?16 (5?8, so -8) are shorted together to form the second terminal. the parameters are then measured between these two terminals. 3. measured from input pin to ground. table 8. iec 60664-1 (vde 0884 part 2) ratings parameter test conditions specification basic isolation group material group iiia installation classification rated mains voltages < 150 v rms i-iv rated mains voltages < 300 v rms i-iii rated mains voltages < 400 v rms i-ii
si840x 12 rev. 1.2 table 9. iec 60747-5-2 insulation characteristics for si84xxxb* parameter symbol test condition characteristic unit maximum working insulation voltage v iorm 560 v peak input to output test voltage v pr method a after environmental tests subgroup 1 (v iorm x1.6=v pr , t m =60sec, partial discharge < 5 pc) 896 v peak method b1 (v iorm x1.875=v pr , 100% production test, t m =1 sec, partial discharge < 5 pc) 1050 after input and/ or safety test subgroup 2/3 (v iorm x1.2=v pr , t m =60sec, partial discharge < 5 pc) 672 highest allowable over voltage (transient overvoltage, t tr =10 sec) v tr 4000 v peak pollution degree (din vde 0110, table 1) 2 insulation resistance at t s , v io =500v r s >10 9 ? *note: the si840x is suitable for basic electrical isolation within the safety limit data. maintenance of the safety data is ensured by protective circuits. the si840x prov ides a climate classification of 40/125/21. table 10. iec safety limiting values 1 parameter symbol test condition nb soic-8 nb soic-16 unit case temperature t s 150 150 c safety input current i s ? ja =105c/w (nb soic-16), 140 c/w (nb soic-8) avdd, bvdd = 5.5 v, t j =150c, t a =25c 160 210 ma device power dissipation 2 p d 220 275 w notes: 1. maximum value allowed in the event of a failure. refe r to the thermal derating curve in figure 8 and figure 9. 2. the si840x is tested with avdd, bvdd = 5.5 v; t j = 150 oc; c 1 , c 2 =0.1f; c 3 = 15 pf; r1, r2 = 3k ??? input 1 mhz 50% duty cycle square wave.
si840x rev. 1.2 13 figure 8. nb soic-8 thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 figure 9. nb soic-16 thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 table 11. thermal characteristics parameter symbol test condition nb soic-8 nb soic-16 unit ic junction-to-air thermal resistance ? ja 140 105 c/w 0 200 150 100 50 400 200 100 0 case temperature (oc) safety-limiting values (ma) 300 avdd, bvdd = 3.6 v avdd, bvdd = 5.5 v 270 160 02 0 0 150 100 50 500 400 200 100 0 temperature (oc) safety-limiting current (ma) 300 350 210 avdd , bvdd = 3.6 v avdd , bvdd = 5.5 v
si840x 14 rev. 1.2 2. overview 2.1. theory of operation the operation of an si84xx channel is analogous to that of an opto coupler, except an rf carrier is modulated instead of light. this simple archit ecture provides a robust isolated data path and requires no special considerations or initialization at st art-up. a simplified block diagram for a single unidirectional si84xx channel is shown in figure 10. figure 10. simplified channel diagram a channel consists of an rf transmitter and rf receiver separated by a semiconductor-based isolation barrier. referring to the transmitter, input a modulates the carrier provided by an rf oscillator using on/off keying. the receiver contains a demodulator that decodes the input state according to its rf energy content and applies the result to output b via the output driv er. this rf on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consum ption, and better immunity to magnetic fields. see figure 11 for more details. figure 11. modulation scheme rf oscillator modulator demodulator a b semiconductor- based isolation barrier transmitter receiver input signal output signal modulation signal
si840x rev. 1.2 15 3. device operation device behavior during start-up, normal operation, and shutdown is shown in figure 12, where uvlo+ and uvlo- are the positive-going and negative-going thresholds resp ectively. refer to table 12 to determine outputs when power supply (vdd) is not present. 3.1. device startup outputs are held low during powerup until vdd is above the uvlo threshold for time period tstart. following this, the outputs follow the states of inputs. 3.2. under voltage lockout under voltage lockout (uvlo) is provided to prevent erroneous operation during device startup and shutdown or when vdd is below its specified operating circuits r ange. both side a and side b each have their own under voltage lockout monitors. each side can enter or exit uvlo independently. for example, side a unconditionally enters uvlo when avdd falls below avdd uvlo? and exits uvlo when avdd rises above avdd uvlo+ . side b operates the same as side a with respect to its bvdd supply. figure 12. device behavior during normal operation input avdd uvlo- bvdd uvlo+ uvlo- uvlo+ output tstart tstart tstart tphl tplh tsd
si840x 16 rev. 1.2 3.3. input and output characteristics for non-i 2 c digital channels the si84xx inputs and outputs are standard cmos drivers/ receivers. the nominal outpu t impedance of an isolator driver channel is approximately 85 ? , 40%, which is a combination of the va lue of the on-chip series termination resistor and channel resistance of the output driver fet. when driving load s where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. table 12 details powered and unpowered operation of the si84xx?s non-i 2 c digital channels. table 12. si84xx operation table v i input 1, 4 vddi state 1,2,3 vddo state 1,2,3 v o output 1, 4 comments hp p h normal operation. lp p l xup p l upon transition of vddi from unpowered to pow- ered, v o returns to the same state as v i in less than 1 s. x p up undetermined upon transition of vddo from unpowered to pow- ered, v o returns to the same state as v i within 1s. notes: 1. vddi and vddo are the input and output power supplies. v i and v o are the respective input and output terminals. 2. powered (p) state is defined as 3.0 v < vdd < 5.5 v. 3. unpowered (up) state is defined as vdd = 0 v. 4. x = not applicable; h = logic high; l = logic low.
si840x rev. 1.2 17 4. layout recommendations dielectric isolation is a set of specific ations produced by safety regulatory agencies from around the world, which describes the physical construction of electrical equipment that derives power from high-voltage power systems, such as 100?240 v ac systems or industrial power. the dielectric test (or hipot test) given in the safety specifications places a very high voltage between the input power pins of a product an d the user circuits and the user-touchable surfaces of the product. for the iec rela ting to products deriving their power from the 100?240 v ac power grids, the minimum test voltage is 2500 v ac (or 3750 v dc , the peak equivalent voltage). there are two terms described in the safety specifications: ? creepage?the distance along the insulating surface an arc may travel. ? clearance?the shortest distance through air that an arc may travel. figure 13 illustrates the accepted met hod of providing the pro per creepage distance along the surface. for a 120 v ac application, this distance is 3.2 mm, and the na rrow-body soic package can be used. for a 220?240 v ac application, this distance is 6.4 mm, and a wide-body soic package must be used. there must be no copper traces within this 3.2 or 6.4 mm exclusion area, and the surface should have a conforma l coating, such as solder resist. the digital isolator chip must straddle this exclusion area. figure 13. creepage distance 4.1. supply bypass the si84xx families require a 1 f bypass capacito r between avdd and agnd and bvdd and bgnd. the capacitor should be placed as close as possible to th e package. see "6.errata and design migration guidelines (revision a only)" on page 22 for more details. iec specified creepage distance
si840x 18 rev. 1.2 4.2. rf radiated emissions the si84xx families use an rf carrie r frequency of approximately 700 mhz. this results in a small amount of radiated emissions at this frequency and its harmonics. the radi ation is not from the ic but, rather, is due to a small amount of rf energy driving the isolated grou nd planes, which can act as a dipole antenna. the unshielded si84xx evaluation board passes fcc class b (part 15) requirements. table 13 shows measured emissions compared to fcc requirements. note that the da ta reflects worst-case conditions, where all inputs tied to logic 1 and the rf tran smitters are fully active. radiated emissions can be reduced if the circuit board is enclosed in a shielded enclosure or if the pcb is a less efficient antenna. 4.3. rf, magnetic, and co mmon mode transient immunity the si84xx families have very high common mode transient immunity while transmitting data. this is typically measured by applying a square pulse with very fast rise/fall times between the isolated grounds. measurements show no failures at 25 kv/s (typical). during a high surg e event, the output may glitch low for up to 20?30 ns, but the output corrects immediately after the surge event. the si84xx families pass the industrial requirements of cispr24 for rf immu nity of 10 v/m using an unshielded evaluation board. as shown in figure 14, the isolated ground planes form a parasitic dipole antenna. the pcb should be laid-out to not act as an ef ficient antenna for the rf frequency of interest. rf susceptibility is also significantly reduced when the end system is hous ed in a metal enclosure, or otherwise shielded. the si840x digital isolator can be us ed in close proximity to large moto rs and various other magnetic-field producing equipment. in theory, data transmission errors can occur if the magnetic field is too large and the field is too close to the isolator. however, in actual use, the si84xx devices provide extremely high immunity to external magnetic fields and have been indepe ndently evaluated to withstand magn etic fields of at least 1000 a/m according to the iec 61000-4-8 and iec 61000-4-9 specifications. figure 14. dipole antenna table 13. radiated emissions frequency (mhz) measured (dbv/m) fcc spec (dbv/m) compared to spec (db) 712 29 37 ?8 1424 39 54 ?15 2136 42 54 ?12 2848 43 54 ?11 4272 44 54 ?10 4984 44 54 ?10 5696 44 54 ?10 isolator gnd1 gnd2 dipole antenna
si840x rev. 1.2 19 5. typical application overview 5.1. i 2 c background in many applications, i 2 c, smbus, and pmbus interfaces require galvanic isolation for safety or ground loop elimination. for example, power over ether net (poe) applications typically use an i 2 c interface for communication between the poe power sourcing device (pse), and the earth ground referenced system controller. galvanic isolation is required both by standard and also as a prac tical matter to prevent ground loops in ethernet connected equipment. the physical interface consists of tw o wires: serial data (sda) and serial clock (scl). these wires are connected to open collector drivers that serve as both inputs and out puts. at first glance, it appears that sda and scl can be isolated simply by placing two unidirectional isolators in parallel, and in opposite directions. however, this technique creates feedback that latches the bus line low when a logic low asserted by ei ther master or slave. this problem can be remedied by adding anti-latch circuits, bu t results in a larger and more expensive solution. the si840x products offer a single-chip, anti-l atch solution to the problem of isolating i 2 c/smbus applications and require no external components except the i 2 c/smbus pull-up resistors. in addi tion, they provide isolation to a maximum of 2.5 kv rms , support i 2 c clock stretching, and operate to a maximum i 2 c bus speed of 1.7 mbps. 5.2. i 2 c isolator operation without anti-latch protection, bidirectional i 2 c isolators latch when an isolator output logic low propagates back through an adjacent isolator channel creating a stable latched low condition on both sides. anti-latch protection is typically added to one side of the isolator to avoi d this condition (the "a" si de for the si8400/01/05). the following examples illustrate typical circ uit configurations using the si8400/01/05. figure 15. isolated bus overview the "a side" output low (v ol ) and input low (v il ) levels are designed such that the isolator v ol is greater than the isolator v il to prevent the latch condition. i2c/smbus unit 1 si8400/01/05 i 2 c/smbus unit 2 iso1 iso2 v ol v il + - v ol v il a side b side
si840x 20 rev. 1.2 5.3. i 2 c isolator design constraints table 14 lists the design constraints. 5.4. i 2 c isolator design considerations the first step in applying an i 2 c isolator is to choose which side of the bus will be connected to the isolator a side. ideally, it should be the side which: 1. is compatible with the range of bus pull up specified by the manufacturer. for example, the si8400/01/05 isolators are normally used with a pull up of 0.5 ma to 3 ma. 2. has the highest input low level for devices on the bu s. some devices may specif y an input low of 0.9 v and other devices might require an input low of 0.3 x vdd. assuming a 3.3 v minimum power supply, the side with an input low of 0.3 x vdd is the better side bec ause this side has an input low level of 1.0 v. 3. have devices on the bus that can pull down below the is olator input low level. for example, the si840x input level is 0.45 v. as most cmos devices can pull to within 0.4 v of gnd this is generally not an issue. 4. has the lowest noise. due to the special logi c levels, noise margins can be as low as 50 mv. the si840x isolators are not compatible with devices that have a logic low of 0.8 v. for this situation, a discrete circuit can be used. see ?an352: low-cost, high-speed i 2 c isolation with digital isolators? for additional information. table 14. design constraints design constraint data sheet values effect of bus pull-up strength and temperature to prevent the latch condition, the isolator output low level must be greater than the isolator input low level. isolator v ol 0.8 v typical isolator v il 0.6 v typical input/output logic low level difference vsda1, vscl1 = 50 mv minimum this is normally guaranteed by the isolator data sheet. however, if the pull up strength is too weak, the out- put low voltage will fall and can get too close to the input low logic level. these track over temperature. the bus output low must be less than the isolator input low logic level. bus v ol =0.4v maximum isolator v il = 0.45 v minimum if the pull up streng th is too large, the devices on the bus might not pull the voltage below the input low range. these have opposite temper- ature coefficients. worst case is hot temperature. the isolator output low must be less than the bus input low. bus v il 0.3 x v dd = 1.0 v minimum for v dd =3.3v isolator v ol = 0.825 v maximum, (0.5 ma pullup, ?10 to 125 c) if the pull up streng th is too large, the isolator might not pull below the bus input low voltage. si8400/01/05 vol: ?1.8 mv/c cmos buffer: ?0.6 mv/c this provides some temperature tracking, but worst case is cold tem- perature.
si840x rev. 1.2 21 figures 16, 17, and 18 illustrate ty pical circuit configurations usin g the si8400, si 8401, and si8405. figure 16. typical si8400 application diagram figure 17. typical si8401 application diagram figure 18. typical si8405 application diagram 1 2 7 si8400 3 8 avdd asda ascl agnd bgnd bscl bsda bvdd 3k 3k 0.1 f 0.1 f 3k 3k i 2 c bus 6 5 4 1 2 7 si8401 3 8 avdd asda ascl agnd bgnd bscl bsda bvdd 3k 3k 0.1 f 0.1 f 3k i 2 c bus 6 5 4 1 2 3 4 5 6 7 15 14 13 12 11 10 8 9 si8405 3 16 avdd asda ascl agnd micro- controller micro- controller bgnd bscl bsda bvdd 3k 3k 0.1 f 0.1 f 3k 3k i 2 c bus reset int
si840x 22 rev. 1.2 6. errata and design migration guidelines (revision a only) the following errata apply to revision a devices only. see "8.ordering guide" on page 25 for more details. no errata exist for revision b devices. 6.1. power supply bypass ca pacitors (revision a only) when using the isopro isolators with power supplies > 4.5 v, sufficient vdd bypass capacitors must be present on both the vdd1 and vdd2 pins to ensure the vdd rise time is less than 0.5 v/ s (which is > 9 s for a > 4.5 v supply). although rise time is power supply dependent, > 1 f capacitors are required on both power supply pins (vdd1, vdd2) of the isolator device. 6.1.1. resolution this issue has been corrected with revision b of the device. refer to ?8. ordering guide? for current ordering information.
si840x rev. 1.2 23 7. pin descriptions table 15. si8400/01 in so-8 package pin name description 1 avdd side a power supply terminal; c onnect to a source of 3.0 to 5.5 v. 2 asda side a data input or output. 3 ascl side a clock input or output (si8400); side a clock input (si8401). 4 agnd side a ground terminal. 5 bgnd side b ground terminal. 6 bscl side b clock input or output (si8400); side b clock output (si8401). 7 bsda side b data input or output. 8 bvdd side b power supply terminal; connect to a source of 3.0 to 5.5 v. 1 4 3 asda bsda ascl bscl agnd bgnd avdd bvdd 2 8 5 6 7 si8400/01
si840x 24 rev. 1.2 table 16. si8405 in narrow-body so-16 package pin name description 1 avdd side a power supply terminal. connect to a source of 3.0 to 5.5 v. 2 nc no connection. 3 asda side a data input or output. 4adin side a digital input (non i 2 c). 5 adout side a digital output (non i 2 c). 6 ascl side a clock input or output. 7 nc no connection. 8 agnd side a ground terminal. 9 bgnd side b ground terminal. 10 nc no connection. 11 bscl side b clock input or output. 12 bdin side b digital input (non i 2 c). 13 bdout side b digital output (non i 2 c). 14 bsda side b data input or output. 15 nc no connection. 16 bvdd side b power supply terminal. connect to a source of 3.0 to 5.5 v. avdd nc bvdd nc nc nc adout bdin asda bsda ascl bscl 1 2 3 4 5 6 7 15 14 13 12 11 10 adin bdout 8 9 si8405 agnd bgnd 3 16
si840x rev. 1.2 25 8. ordering guide revision b devices are recommended for all new designs. figure 19. naming convention table 17. ordering guide 1 ordering part number number of bidirection al i 2 c channels max i 2 c bus speed (mhz) number of unidirectional channels max data rate of non-i 2 c unidirectional channels (mbps) isolation ratings temp range (?c) package si8400aa-b-is 2 1.7 0 ? 1 kv rms ?40 to 125 nb soic-8 si8400ab-b-is 2 1.7 0 ? 2.5 kv rms ?40 to 125 nb soic-8 si8401aa-b-is 1 1.7 1 ? 1 kv rms ?40 to 125 nb soic-8 si8401ab-b-is 1 1.7 1 ? 2.5 kv rms ?40 to 125 nb soic-8 si8405aa-b-is1 2 1.7 1 forward 1 reverse 10 1 kv rms ?40 to 125 nb soic-16 si8405ab-b-is1 2 1.7 1 forward 1 reverse 10 2.5 kv rms ?40 to 125 nb soic-16 revision a devices 2 si8400aa-a-is 2 21.7 0 ? 1kv rms ?40 to 125 nb soic-8 SI8400AB-A-IS 2 21.7 0 ?2.5kv rms ?40 to 125 nb soic-8 si8405aa-a-is1 2 21.7 1 forward 1 reverse 10 1 kv rms ?40 to 125 nb soic-16 si8405ab-a-is1 2 21.7 1 forward 1 reverse 10 2.5 kv rms ?40 to 125 nb soic-16 notes: 1. all packages are rohs-compliant. moisture sensitivity le vel is msl2a with peak reflow temperature of 260 c according to the jedec industry standard classifications and peak solder temperature. 2. revision a devices are supported for existing designs, but revision b is recommended for all new designs. si840ysv-r-tpn isolator product i 2 c isolator series channel config (0 = bidi. scl, sda 1 = bidi. sda; uni. scl 5 = bidi. scl, sda; uni. 1-fwd, 1-rev.) max data rate (a = 1.7 mbps) insulation rating (a = 1 kv; b = 2.5 kv) product revision temp range (i = -40 to +125c) package type (s = soic) package extension (1 = narrow body - 16 pin only)
si840x 26 rev. 1.2 9. package outline: 8-pin narrow body soic figure 20 illustrates the package details for the si840x in an 8- pin soic (so-8). table 18 lists the values for the dimensions shown in the illustration. figure 20. 8-pin small outline integrated circuit (soic) package table 18. package diagram dimensions symbol millimeters min max a 1.35 1.75 a1 0.10 0.25 a2 1.40 ref 1.55 ref b 0.33 0.51 c 0.19 0.25 d 4.80 5.00 e 3.80 4.00 e 1.27 bsc h 5.80 6.20 h 0.25 0.50 l 0.40 1.27 ? 0 ? 8 ? ?
si840x rev. 1.2 27 10. landing pattern: 8-pin narrow body soic figure 21 illustrates the recommended landing pattern details for the si840 x in an 8-pin narrow-body soic. table 19 lists the values for the di mensions shown in the illustration. figure 21. pcb landing pattern: 8-pin narrow body soic table 19. pcm landing pattern dimensions (8-pin narrow body soic) dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p600x173-8n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
si840x 28 rev. 1.2 11. package outline: 16-pin narrow body soic figure 22 illustrates the package details for the si840x in a 16-pin narrow-b ody soic (so-16). table 20 lists the values for the di mensions shown in the illustration. figure 22. 16-pin small outline integrated circuit (soic) package table 20. package diagram dimensions dimension min max a ? 1.75 a1 0.10 0.25 a2 1.25 ? b 0.31 0.51 c 0.17 0.25 d 9.90 bsc e 6.00 bsc e1 3.90 bsc e 1.27 bsc l 0.40 1.27 l2 0.25 bsc
si840x rev. 1.2 29 h 0.25 0.50 0 8 aaa 0.10 bbb 0.20 ccc 0.10 ddd 0.25 notes: 1. all dimensions shown are in mill imeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline ms-012, variation ac. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. table 20. package diagram dimensions (continued) dimension min max
si840x 30 rev. 1.2 12. landing pattern: 16-pin narrow body soic figure 23 illustrates the recommended landing pattern details for the si840x in a 16- pin narrow-body soic. table 21 lists the values for the di mensions shown in the illustration. figure 23. 16-pin narrow body soic pcb landing pattern table 21. 16-pin narrow body soic landing pattern dimensions dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p600x165-16n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
si840x rev. 1.2 31 13. top marking: 8-p in narrow body soic figure 24. 8-pin narrow body soic top marking table 22. 8-pin narrow body soic top marking table line 1 marking: base part number ordering options (see ordering guide for more information). si84 = isolator i 2 c product series: ? xy = channel configuration ?? 00 = bidirectional scl and sda channels ?? 01 = bidirectional sda channel; unidirectional scl channel ? s = speed grade ?? a=1.7mbps ? v = isolation rating ?? a=1kv; b=2.5kv line 2 marking: yy = year ww = work week assigned by assembly contractor. corresponds to the year and work week of the mold date. r = product rev f=wafer fab first two characters of the manufacturing code from assembly. line 3 marking: circle = 1.1 mm diameter left-justified ?e3? pb-free symbol a = assembly site i = internal code xx = serial lot number last four characters of the manufacturing code from assembly. si84xysv yywwrf aixx e3
si840x 32 rev. 1.2 14. top marking: 16-pin narrow body soic figure 25. 16-pin narrow body soic top marking table 23. 16-pin narrow body soic top marking table line 1 marking: base part number ordering options si84 = isolator product series ? xy = channel configuration ?? 05 = bidirectional scl, sda; 1- forward and 1-reverse unidirectional channel ? s = speed grade ?? a=1.7mbps ? v = isolation rating ?? a=1kv; b=2.5kv line 2 marking: circle = 1.2 mm diameter ?e3? pb-free symbol yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the mold date. tttttt = mfg code manufacturing code from assembly purchase order form. circle = 1.2 mm diameter ?e3? pb-free symbol. si84xysv yywwtttttt e3
si840x rev. 1.2 33 d ocument c hange l ist revision 0.1 to revision 1.0 ? updated document to reflect availability of revision b silicon. ? updated tables 1, 2, 3, and 4. ?? updated all supply currents and timing parameters. ?? revised logic low output vo ltage specifications in table 2. ? updated table 5. ?? updated absolute maximum supply voltage. ? updated table 7. ?? updated clearance and creepage dimensions. ? updated "6.errata and design migration guidelines (revision a only)" on page 22. ? updated "8.ordering guide" on page 25. revision 1.0 to revision 1.1 ? updated table 3. ?? updated note 1 to reflect output impedance of 85 ? . ?? updated rise and fall time specifications. ? updated table 4. ?? updated cmti value. ? updated ?8. ordering guide?. ? added si8401 device configuration throughout document. revision 1.1 to revision 1.2 ? updated document throughout to include msl improvements to msl2a. ? updated "8.ordering guide" on page 25. ?? updated note 1 in ordering guide table to reflect improvement and compliance to msl2a moisture sensitivity level.
si840x 34 rev. 1.2 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believ ed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including without limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon labor atories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. the sale of this product contains no licens es to power-one?s intellectual property. contact power-one, inc. for appropriate lic enses.

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